Zero string error detection circuit

ABSTRACT

A zero string error detection circuit which detects a specified number of zeros occurring in succession in bipolar data. The detection circuit has a relatively small gate size achieved by making the shift registers in the B8ZS or B6ZS code conversion circuit serve also for zero string monitoring. The zero string error detection circuit includes a pair of shift registers which receive serial bipolar data and convert it to parallel data composed of a specified number of bits, a code detector which, upon detecting a specific code from the parallel outputs of the shift registers, issues a reset signal to the shift registers to make the outputs of the shift registers zero, a zero string monitor which issue a zero string error detection signal when the outputs of the shift registers become zero, and a gate which inhibits the zero string monitor from issuing the zero string error detection signal during a specific period when the code detector issues a reset signal.

BACKGROUND OF THE INVENTION

1. Field of the Invention

This invention concerns a zero string error detection circuit whichdetects a string of zeros in bipolar data.

In digital transmission for audio data and other data, for example, theclock for playback synchronization and data recognition is extractedfrom the audio data. The clock cannot be extracted if zeros occur insuccession as in the condition of no sound. If data is transmitted in8-bit units, eight successive zeros are converted to an 8-bit code (B8ZScode) in a specific pattern. If data is transmitted in 6-bit units, sixsuccessive zeros are converted to a 6-bit code (B6ZS code) in a specificpattern.

At the receiving end, this code, when detected, is returned to theoriginal string of zeros. This means that normally, no zero signalshould be detected during the period from the time of conversion at thetransmitting end to the time of restoration at the receiving end.

However, when a fault occurs in the transmission path or otherfacilities, zero signals may occur. Therefore, transmission systems aredesigned so that when a specified number of zero bits are detected, asignal indicating a zero string error (zero string error detectionsignal) is issued and when the zero string error detection signal isissued a number of times in succession, an alarm is issued to thetransmitting end.

2. Description of the Related Art

FIG. 6 is a circuit diagram of a conventional zero string errordetection circuit. In this figure, 1P and 1N represent shift registers.Shift register 1P receives the positive side of serial bipolar data Pand converts it to parallel data composed of a specific number (8, forexample) of bits. Shift register 1P receives the negative side of serialbipolar data N and converts it to parallel data composed of a specificnumber (8, for example) of bits.

Component 2 is a B8ZS code detector. When it receives a B8ZS code(000VB0VB, where V is a code which indicates that the data does notconform to the coding rule and B is a code which indicates that the dataconforms to the coding rule--for example, if the output of shiftregister 1P is 00010001 and the output of shift register 1N is 00001010,the B8ZS code is detected) from parallel outputs FF1-FF8 and FF1'-FF8'from the shift registers, it issues a reset signal FRST to shiftregisters 1P and 1N to make the 1P and 1N outputs zero.

Components 3P and 3N are 8-bit zero monitors. Eight-bit zero monitor 3Poutputs a zero string error detection signal when it finds a string ofeight bits of zero in bipolar data P. Eight-bit zero monitor 3N outputsa zero string error detection signal when it finds a string of eightbits of zero in bipolar data N. As indicated in FIG. 7, eight-bit zeromonitors 3P and 3N are fitted with an eight-bit shift register 3P-1(3N-1) and a NOR gate 3P-2 (3N-2) which receives the output of shiftregister 3P-1 (3N-1).

The zero string detection signals are fed via an AND gate to an alarmcontroller which is not shown. When the alarm controller detects thezero string detection signal a specific number of times in succession,it sends an alarm to the transmitting end or other components.

Component 5 is an OR gate for extracting output data. It receives thesixth outputs FF6 and FF6' of shift registers 1P and 1N and outputstheir OR as serial data.

When B8ZS code detector 2 detects a B8ZS code in outputs from shiftregisters 1P and 1N in the above configuration, it issues a reset signalFRST to shift registers 1P and 1N to make the outputs of shift registers1P and 1N zero. As a consequence, the B8ZS code is returned to eightbits of zero.

If zeros occur in succession because of a fault in the transmission pathor other components, eight-bit zero monitors 3P and 3N issue zero stringerror detection signals, respectively. If the zero string errordetection signals are issued a number of times in succession, the alarmcontroller issues an alarm to the transmitting end.

Zero string error detection systems where a B6ZS code is detected havesimilar configurations and functions.

The above conventional zero string error detection circuit with a B8ZScode converter involves a problem that a large-scale gate circuit mustbe used because zero strings are detected both in bipolar data P and inbipolar data N.

A similar problem is involved in a zero string error detection circuitwhich handles B6ZS codes.

SUMMARY OF THE INVENTION

This invention has been made considering the above problem. It isintended to provide a zero string error detection circuit characterizedby a relatively small gate size achieved by making the shift register inthe B8ZS or B6ZS code converter serve also to monitor strings of zeros.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram of a zero string detection circuit accordingto the present invention.

FIG. 2 is a circuit diagram of an embodiment according to the presentinvention.

FIG. 3 is a detailed circuit diagram showing a principal part of theembodiment of the present invention;

FIG. 4, including FIGS. 4(a)-4(c), is a timing chart illustrating theprocedure for mask signal generation;

FIG. 5, including FIGS. 5(a)-5(c), is a timing chart illustrating thefunction available in the embodiment of the present invention;

FIG. 6 is an electric circuit diagram of a prior art zero stringdetection circuit;

FIG. 7 is a circuit diagram of a prior art eight-bit zero monitor.

DESCRIPTION OF THE PREFERRED EMBODIMENT OF THE INVENTION

FIG. 1 is a block diagram of a zero string detection circuit accordingto the present invention.

In FIG. 1, components 1P and 1N are a pair of shift registers whichreceive positive side bipolar data P and negative side of bipolar data Nrespectively which are input serially. The shift registers convert theserial data to parallel data having n bits (where n is a naturalnumber). Component 2 is a code detector which, upon receiving a specificcode in parallel outputs from shift registers 1P and 1N, issues a resetsignal FRST to shift registers 1P and 1N to make the outputs of shiftregisters 1P and 1N zero.

Component 3 is a zero string monitor which issues a zero string errordetection signal when the parallel outputs of shift registers 1P and 1Nbecome zero. Component 6 is a gate which, upon receiving the resetsignal FRST from code detector 2, inhibits zero string monitor 3 fromissuing a zero string error detection signal during a specific period.

Component 5 is an OR gate for extracting output data.

When code detector 2 detects a specific code in the outputs of shiftregisters 1P and 1N in the above configuration, it issues the resetsignal FRST to shift registers 1P and 1N to make the outputs of shiftregisters 1P and 1N zero. As a consequence, the specific code isreturned to the original number of zero bits.

Upon receiving the reset signal FSRT from code detector 2, gate 6inhibits zero string monitor 3 from issuing the zero string errordetection signal during a specific period. During this period, no alarmis issued to the transmitting end even when a zero string is detected.

If zeros occur in succession because of a fault in the transmission pathor other components, zero string monitor 3 issues a zero stringdetection error signal. Since code detector 2 does not issue a resetsignal FRST even when the zero string continues, the mask function ofgate 6 is disabled. If the zero string error detection signal is issueda number of times in succession, an alarm or other information is issuedto the transmitting end.

FIG. 2 is a block diagram of an embodiment according to the presentinvention. In FIG. 2, components 1P and 1N are shift registers,component 2 is a B8ZS code detector, and component 3 is an eight-bitzero monitor.

Shift registers 1P and 1N and B8ZS code detector 2 are the same as thosein the conventional circuit shown in FIG. 6. Therefore, their detailedexplanation is omitted here.

Eight-bit zero monitor 3 issues a zero string error detection signalwhen the parallel outputs FF1-FF8 and FF1'-FF8' of shift registers 1Pand 1N become zero. As indicated in FIG. 3, it is fitted with a 16-inputNOR gate 3A which receives parallel outputs FF1-FF8 and FF1'-FF8' fromshift registers 1P and 1N.

In addition, gate 6B is provided to inhibit eight-bit zero monitor 3from issuing a zero string error detection signal during a specifiedperiod (corresponding to eight clock cycles) when the reset signal FRSTis output from B8ZS code detector 2.

When B8ZS code detector 2 issues a reset signal FRST, mask patterngenerator 6A outputs a mask signal MSK during the above period. Asindicated in FIG. 3, its circuit is a combination of a frequency dividerfitted with four flip-flops 6A-1, 6A-2, 6A-3, and 6A-4 and an inverter6A-5. FIGS. 4(a)-(4e) show the waveforms of the clock input to maskpattern generator 6A and other signals.

In FIG. 2, component 5 is an OR gate for extracting output data fromsixth outputs FF6 and FF6' of shift registers 1P and 1N.

When B8ZS code detector 2 detects a B8ZS code in the outputs of shiftregisters 1P and 1N in the above configuration, it issues the resetsignal FRST to shift registers 1P and 1N to make the output of shiftregisters 1P and 1N zero. As a consequence, the B8ZS code is returned toeight bits of zero.

When B8ZS code detector 2 issues the reset signal FRST, mask patterngenerator 6A outputs the mask signal MSK to AND gate 6B during eightclock cycles. This inhibits eight-bit zero monitor 3 from outputting thezero string error detection signal. Therefore, an alarm or otherinformation indicating the detection of a zero string is not issued tothe transmitting end.

If zeros occur in succession because of a fault in the transmission pathor other components, eight-bit zero monitor 3 issues a zero string errordetection signal. However, B8ZS code detector does not issue a resetsignal FRST even when the zero string continues. Therefore, the maskfunction of gate 6 containing mask pattern generator 6A is disabled. Ifthe zero string error detection signal is issued a number of times insuccession, an alarm controller (not shown) which has received thosedetection signals issues an alarm and other information to thetransmitting end.

FIGS. 5(a)-5(o) are timing charts which apply to the aboveimplementation sample. FIG. 5(a) is the waveform of a clock CLK(synchronized with clock XCLK) supplied to shift registers 1P and 1N;FIGS. 5(b) and 5(c) show states 0 and 1 of the positive and negativeside of bipolar data P and N; FIG. 3(d) shows the combination of thepositive and negative side of bipolar data P and N; FIG. 5(e)-5(l) showoutputs FF1-FF8 (FF1'-FF8') of shift register 1P (1N); FIG. 5(m) showsthe waveform of the zero string error detection signal; FIG. (n) is atiming chart for B8ZS code detection; FIG. 3(o) is a timing chart forthe reset signal FRST output.

FIG. 5(d) shows data which is obtained when the data P and data N shownin FIGS. 5(b) and 5(c) respectively, are combined. For simplification,this will be explained supposing that the data is serially input toshift registers 1P and 1N and output in parallel.

Entering all data into shift registers 1P and 1N results in outputtingin parallel as shown in FIG. 5(e)-FIG. 5(l). This output is entered intoB8ZS code detector 2 and detected as codes. Actually, the paralleloutputs of data P and data N shown in FIGS. 5(b) and FIG. 5(c) aredesigned to be subjected to code detection respectively as shown in FIG.5(o).

When data indicating all "0's" is converted into parallel data by shiftregisters 1P and 1N, a detection signal is output as shown in FIG. 5(n),followed by reset signals issued to shift registers 1P and 1N. Then,shift registers FF1-FF8 (FF1'-FF8') output 0 only. As shown in FIG. 5(m)by a two-dot and dash line as "Zero string error detection mask", a masksignal is issued.

The mask signal itself has a width of only 7 bits, because the finaloutput is obtained from the output FF6 (FF6'). More specifically, thecode indicating all "0's" is "000VB0VB", and when all zeroes aredetected, output "0" has already been obtained from the output FF6(FF6').

Meanwhile, when 8 bits of zero are entered in shift registers 1P and 1N,the detection signal is issued as shown in FIG. 5(m).

The gate size can be made much smaller than in the conventional circuitbecause shift registers 1P and 1N in the B8ZS code conversion circuitcan also be used for eight-bit zero monitoring.

Obviously, this invention is applicable to zero string error detectioncircuits which detect a B6ZS code.

It is to be understood that the foregoing description is merelyillustrative of the preferred embodiments of the present invention, andthat the present invention is not to be limited thereto, but is to bedetermined by the scope of the appended claims.

What is claimed is:
 1. A zero string error detection circuitcomprising:a pair of shift registers for serially receiving,respectively, a positive side and negative side of bipolar data,converting it to parallel data composed of a required number of bits andoutputting the parallel data, the output parallel data comprisingcurrent signals from a transmission line; a code detector, operativelyconnected to said pair of shift registers for receiving the outputparallel data, said code detector, upon detecting a specific code in theparallel outputs of said shift registers, outputting a reset signal tosaid shift registers for making the parallel outputs of said shiftregisters zero; a zero string monitor, operatively connected to saidshift registers, for outputting a zero string error detection signalwhen the parallel outputs of said shift registers become zero, said zerostring monitor including a NOR GATE for receiving the output paralleldata from said shift registers; and mask pattern generator means,operatively connected to said code detector and said zero stringmonitor, inhibiting said zero string monitor from outputting a zerostring error detection signal during a specific period when said codedetector outputs said reset signal.
 2. A zero string error detectioncircuit according to claim 1, wherein said mask pattern generator meansincludes:a mask pattern generator; and an AND gate operatively connectedto said mask pattern generator and said zero string monitor.
 3. A zerostring error detection circuit according to claim 2, wherein said maskpattern generator has a capability of outputting a mask signal duringthe period said reset signal is output from said code detector.